1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a static random access memory cell having an enhanced cell ratio, and a manufacturing method thereof.
2. Description of the Prior Art
Generally, a Static Random Access Memory (SRAM) has characteristics of high speed, low power consumption, and simple operation, and a SRAM memory cell usually consists of a flip-flop circuit. In addition, unlike a DRAM, the SRAM has advantages of an easy design as well as not having to regularly refresh stored data. In general, the SRAM cell includes: two pull-up transistors; two access transistors; and two pull-down transistors. The SRAM cell is further classified as the following: a full CMOS cell; a high road resistor(HRL) cell; and a thin film transistor (TFT) cell in accordance with the load type of the pull-up transistors.
The TFT cell is a memory cell wherein a P channel polysilicon TFT is used as a load transistor. A SRAM with TFT cell is developed for a 4 Mb or a 16 Mb SRAM cell. Compared to a SRAM with HRL cell, the SRAM with TFT cell has lower standby power consumption and has excellent stability. In addition, compared to a SRAM with the full CMOS cell having a bulk structure, the SRAM with the TFT cell has an excellent degree of high integration. However, the manufacturing process of the SRAM with the TFT cell is complex. Accordingly, the SRAM with the full CMOS cell having the bulk structure is manufactured and utilized to a higher degree. In contrast to the SRAM with the TFT cell, the SRAM with the full CMOS cell can be fabricated with a simple process. In addition, the SRAM with the full CMOS cell is possible to obtain a high current during its operation.
FIG. 1 illustrates a circuit diagram of a SRAM cell with the full CMOS cell.
Referring to FIG. 1, reference numerals WL denotes a word line, BL1 and BL2 denote bit lines, N1 and N2 denote nodes, VDD denotes a power supply voltage, and VSS denotes a ground voltage respectively. Reference numerals UT1 and UT2 denote P channel MOS(PMOS) transistors for use in pull-up devices, DT1 and DT2 denote N chanel MOS(NMOS) transistors for use in pull-down devices, and AT1 and AT2 denote NMOS transistors for use in access devices, respectively.
A first CMOS inverter is consisted of the PMOS transistor UT1 for use in pull-up device and the NMOS transistor DT1 for use in pull-down. A second CMOS inverter is consisted of the PMOS transistor UT2 for use in pull-up device and the NMOS transistor DT2 for use in pull-down device. At the cell node N1, the output of the first CMOS inverter and the input of the second CMOS inverter are connected to each other. At the cell node N2, the input of the first CMOS inverter and the output of the second CMOS inverter are connected to each other. The sources of the NMOS transistor AT1 and AT2 for use in access devices are respectively connected to the bit line BL1 and BL2. The drains of the NMOS transistor AT1 and AT2 for use in access devices are respectively connected to the cell node N1 and N2. The gates of the NMOS transistor AT1 and AT2 for use in access devices are connected to the word line WL.
In the SRAM cell having the above described structure, in order to store data at a HIGH state in the cell node N1 and data at a LOW state in the cell node N2, the NMOS transistors AT1 and AT2 are turned by turning on the word line WL. Data at a HIGH state is inputted to the bit line BL1 and data at a LOW state is inputted to the bit line BL2, so that the PMOS transistor UT1 and the NMOS transistor DT2 are turned on, and the PMOS transistor UT2 and the NMOS transistor DT1 are turned off. As a result, the cell node N1 becomes a HIGH state and the cell node N2 becomes a LOW state. Furthermore, although the word line WL is turned off, the cell node N1 is maintained at a HIGH state, the cell node N2 is maintained at a LOW state, by latch. Accordingly, data is stored in the cell node N1 and N2 respectively.
Meanwhile, one of the factors determining the characteristics of the SRAM is the current driving capability ratio of the pull-down device, otherwise known as the driving device, and the access device (I.sub.DSAT DRIVER TRANSISTOR /I.sub.DSAT ACCESS TRANSISTOR), otherwise known as cell ratio. A higher cell ratio results in improved performance of the SRAM. Therefore when the current amount of the pull-down device is larger and the current amount access device is small, the performance of the SRAM cell is improved.
Hereinbelow, the operation of the SRAM cell in relation to the cell ratio will be described with reference to FIG. 1. In case data at a LOW state is stored in the cell node N1 and data at a HIGH state is stored in the cell node N2, the voltage of the cell node N1 is determined by the current amount ratio of the NMOS transistors AT1 and AT2 for use in access devices and the NMOS transistors DT1 and DT2 for use in pull-down devices. Accordingly, when the current amount of the NMOS transistors DT1 and DT2 for use in pull-down devices is increased and the current amount of the NMOS transistors AT1 and AT2 for use in access devices is decreased, the voltage of the cell node N1 is intended to maintain the low voltage. Then, when the NMOS transistors AT1 and AT2 for use in access devices are turned on during a reading operation, the voltage of the cell node N1 does not considerably change at the LOW state regardless of the variation of the voltage of the bit line BL1. If the variation of the voltage of the cell node N1 is small, the voltage of the cross-coupled cell node N2 is maintained at the HIGH state.
Accordingly, in the conventional SRAM cell, the cell ratio is controlled in a manner wherein width of transistor for use in the access device is reduced and its length is increased to thereby reduce its the current amount. In addition, the width of the transistor for use in pull-down device is increased and its length is reduced to thereby increase its the current amount. However, it is impossible to reduce the width and the length of the transistor beyond a predetermined point. Accordingly, there is a limit in relation to the reduction of the cell size for enhancing cell ratio.